Data transmission is an important operation performed by many integrated circuit devices. A phase interpolator is often used to receive data signals, where different phases of a clock signal are used to sample data of a received data stream. The changing of a phase of a clock signal used by the phase interpolator of a receiver to receive data signals may cause output period jitter. Such jitter may be a particular problem in a glitch-sensitive complementary metal oxide semiconductor (CMOS) phase interpolator (PI) device. In data transmission where a clock signal is not sent with the data, a clock recovery circuit is used on the receiving side to derive a clock signal from the incoming data. The phase of the clock signal needs to track any movement in data edges. A clock phase interpolator is often utilized for this purpose. The clock phase interpolator can generate an arbitrary clock phase based on an input digital code. When this code changes, the output clock phase should move. The code may jump by many code steps at a time, often resulting in the output clock having more extended big period jitter than expected.
Circuits and methods for improving the operation of a phase interpolator, such as by reducing jitter, in receiving data are beneficial.